Ultra-Dynamic Voltage Scalable (U-DVS) SRAM Design Considerations

With the continuous scaling down of transistor feature sizes, the semiconductor industry faces new challenges. One of these challenges is the incessant increase of power consumption in integrated circuits. This problem has motivated the industry and academia to pay significant attention to low-power circuit design for the past two decades. Operating digital circuits at lower voltage levels was shown to increase energy efficiency and lower power consumption. Being an integral part of the digital systems, Static Random Access Memories (SRAMs), dominate the power consumption and area of modern integrated circuits. Consequently, designing low-power high density SRAMs operational at low voltage levels is an important research problem. This thesis focuses on and makes several contributions to low-power SRAM design. The trade-offs and potential overheads associated with designing SRAMs for a very large voltage range are analyzed. An 8T SRAM cell is designed and optimized for both sub-threshold and above-threshold operation. Hardware reconfigurability is proposed as a solution to power and area overheads due to peripheral assist circuitry which are necessary for low voltage operation. A 64kbit SRAM has been designed in 65nm CMOS process and the fabricated chip has been tested, demonstrating operation at power supply levels from 0.25V to 1.2V. This is the largest operating voltage range reported in 65nm semiconductor technology node. Additionally, another low voltage SRAM has been designed for the on-chip caches of a low-power H.264 video decoder. Power and performance models of the memories have been developed along with a configurable interface circuit. This custom memory implemented with the low-power architecture of the decoder provides nearly 10X power savings. Thesis Supervisor: Anantha P. Chandrakasan Title: Joseph F. and Nancy P. Keithley Professor of Electrical Engineering